A typical FET assembly includes a gate, a source, and a drain. The gate is conventionally formed from a gate insulator and a gate electrode. The gate insulator may be a layer of silicon oxide (SiO2) or silicon oxynitride (SiON) disposed over a silicon substrate. The gate insulator may be also referred to as a gate dielectric or a gate oxide. The gate electrode may be a layer of poly-crystalline silicon (polysilicon) disposed over the gate insulator. The gate electrode and, optionally, the gate insulator layer may be etched from continuous layers to form an appropriately shaped gate structure.
Silicon oxide and silicon oxynitride (as a gate insulator) and polysilicon (as a gate electrode) have been the standard materials for FETs for many years. As transistors have decreased in size, the thickness of the gate insulators had to decrease steadily as well in order to maintain good electrostatic control over the FET channel. However, with the thinning of the gate insulators comes the problem of leakage currents due to tunneling through the gate insulators formed from silicon oxide.
To further reduce the FET size, new high-K dielectric materials for gate insulators are being introduced. Replacing silicon dioxide with high-K materials reduces the leakage effects mentioned above, while improving electrostatic control over the channel. However, high-K materials present a set of new challenges.